1. Field of the Invention
The present invention relates to semiconductor memory devices and more particularly to a structure and method of producing a non-volatile memory cell with select gate.
2. Background of the Invention
A metal oxide semiconductor ("MOS") transistor generally includes source/drain regions in a substrate, and a gate electrode formed above the substrate between the source/drain regions. A field effect transistor ("FET") is a transistor in which the resistance of the current path from source to drain is modulated by creating an electric field in the substrate by applying a charge on the gate. A simple example of an FET is a select gate or select transistor that consists generally of a polysilicon gate on top of a gate oxide above a substrate, the polysilicon gate coupled to an electrode.
A type of transistor cell that is an integrated circuit memory cell or charge storer is the erasable programmable read-only memory ("EPROM"). EPROMs frequently use memory cells that have electrically isolated gates (floating gates) such as an enhancement-type n-channel metal-oxide semiconductor field effect transistor (MOSFET) with two gates typically of polysilicon material, otherwise known as a Floating Gate Avalanche Injection Metal Oxide Semiconductor (FAMOS) device. In FAMOS technology, information is stored in the memory cells in the form of charge on the floating gates. The EPROM can be programmed by a user, and once programmed, the EPROM retains its data until erased. This type of storage retention is referred to as non-volatile memory.
The EPROM integrated circuit comprises memory cells logically organized by an array of rows and columns. Typically, the rows represent word lines and the columns represent bit lines. By selecting the appropriate word line and bit line, each individual cell may be programmed or read. During the programming operation, a given memory cell or cells are selected for programming, then voltage is applied to the control gate of each memory device (e.g., a FAMOS device). A programming voltage is applied to the bit line of each selected memory cell. The programming voltage generates a programming current flowing through the selected bit line, thus programming the memory cell or cells. The FAMOS memory cell can be in a programmed state wherein the memory cell is not conducting current, or in a "not programmed" state, wherein the memory cell is conducting current.
EPROMs, like FAMOS devices, depend on the long-term retention of electronic charge as the information-storage mechanism. As noted, the charge is stored on a floating polysilicon gate of a MOS device. The term "floating" refers to the fact that no electrical connection exists to this gate. The floating gate is completely surrounded by an insulator, like silicon dioxide, SiO.sub.2. Charge is transferred to the floating gate through the encapsulating layer by the injection of hot electrons. For example, in modern FAMOS technology, the gate, e.g., a control gate insulated from floating gate, and the drain are raised to 12 V while the source and substrate are kept grounded. Hot electrons are created near the drain and these hot electrons are attracted to the floating gate because the floating gate has a more positive potential than the drain. Some of these hot electrons will have enough energy to pass over the insulator oxide and charge the floating gate. Once the hot electrons are transferred to the gate, they are trapped there.
The charge in the floating gate is removed (i.e., the memory is erased) by exposing the EPROM (e.g., a FAMOS transistor) to ultraviolet (UV) light or erasing the EPROM electrically (EEPROM). Exposing the EPROM to UV light permits the simultaneous erasure of all of a memory's array cells that in some applications is desirable. However, EPROMs that require UV light for erasing must be packaged in an expensive ceramic package with a UV-transparent quartz window. In addition, the EPROMs must be removed from the circuit board and put into a special UV eraser to erase the memory.
EEPROMs erase the contents of a ROM electrically. One widely used EEPROM is a floating gate tunneling oxide (FLOTOX) transistor. Programming and erasing of a FLOTOX transistor is done by causing electrons to be transferred from the substrate to the floating gate by a process known as Fowler-Nordheim tunneling, wherein by way of significant voltages (e.g., 12 volts), electrons are transferred from or returned to the substrate by tunneling through a portion of the gate oxide. Because of the high voltages applied to the transistor during erasing, a FLOTOX EEPROM must be isolated by a select transistor. Thus, a FLOTOX EPROM cell consist of two transistors, the memory transistor and a select transistor.
Another type of EEPROM is the flash EEPROM. The flash EEPROM permits the simultaneous erasing of all of the memory's array cells similar to a UV-EPROM. The erasing mechanism of the flash EEPROM can be accomplished in a fashion similar to the FLOTOX by using tunneling off the floating gate to the drain region. Most flash EEPROM configurations incorporate a separate "erase node" into the cell. Such an "erase node" is not art of an FET transistor, but rather just a diffusion area over which the floating gate overlaps. By utilizing an "erase node", the EEPROM device does not need to support the high voltage needed for erasure. Programming of the floating gates of flash EEPROMs is generally accomplished by hot-electron transfer injection into the gate. Selective erasing can also be achieved through the use of the erase node or select gate.
Most FAMOS memory cells that consist of an EEPROM transistor and a select gate use a double-polysilicon FAMOS device with a single polysilicon select gate. The floating layer of polysilicon is isolated by insulating layers between the substrate and the top polysilicon layer. In EPROM technology, the top polysilicon layer is the control gate. The select gate is used to prevent "overerasure" from inhibiting device performance or functionality. After a FAMOS device is erased, the threshold of the device will be reduced. If the device is overerased, excess charge is removed from the gate and the threshold of the device may drop below the intrinsic value, resulting in current conduction even if the control gate voltage is 0 volts. During read operations, this may cause unselected FAMOS devices to allow a current leakage from the bit line that will be misinterpreted by the circuit as an indication that the selected device is conducting or "unprogrammed". Secondly, during the programming, excess leakage from unselected devices may cause a bit line voltage drop that prevents the selected cell from programming. The select gate serves to isolate the FAMOS device from the rest of the array when it is not selected. The isolation avoids the problems discussed. If no select gate is used, complicated and time consuming or iterative erase/program schemes must be used, and new limits are placed on process latitude. For more information on semiconductor memory cells, see S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol. 2, pp. 619-42 (1990).
Another type of integrated circuit that incorporates non-volatile memory but is not an EPROM is a Programmable Logic Device ("PLD"). A PLD is a device for which the logical output is a function of the input. The logic function performed by the device is programmable, possibly through the use of embedded FAMOS devices. A PLD can be made reprogrammable by using a flash cell in the device. In practice, the way a PLD differs from a memory device is that the PLD is "sequential", which means that the outputs are a function of the inputs not only at the present clock cycle, but of the value of inputs at previous clock cycles. Also, because many combination of inputs may not be of interest, for a given number of cells, the PLD has many more inputs than a memory cell, e.g., an EPROM.
FIG. 1(g) is a circuit schematic which shows a typical memory cell in a nonvolatile memory array. The cell includes a float gate field effect transistor (FET) 21 and a select gate field effect transistor 20 coupled in series between a bit line 22 and a reference line (Vss) 23, which is typically ground. It will be appreciated that there are other memory cells (having the same configuration) for different row lines (i.e. other than row line 24) which cells are also coupled between line 22 and line 23. The source/drain current paths of both FETs 21 and 20 are coupled in series such that when the floating gate is not charged from programming, it is possible for current to flow between the bit line 22 and reference line 23. The gate electrode 25 of the select gate FET 20 is coupled to receive the conventional gate signal for the insulated gate of the select gate FET 20. The gate electrode 24 of the floating gate FET 21 is coupled to the conventional row-line in the array of memory cells. It will be appreciated that the select gate FET is designated to help programming, particularly for electrically erasable memory cells. In a memory cell architecture which does not use a select gate FET, if a floating gate FET of a memory cell is overerased, there tends to be a strong "pull-down" during programming from the overerased float gate FET (which is not being programmed), and this tends to reduce current through memory cells which are being programmed. Thus, the select gate FET may be used to solve this overerasing problem by turning off the select gate FET for those memory cells which are not being programmed so that certain desired memory cells on the same bit line as those not being programmed can be programmed. Thus, the select gate FET performs an important function during programming. It will be appreciated that during reading (after programming has been completed), the select gate FET is turned on to allow the floating gate to be "sensed".
Conventional preparation techniques of nonvolatile memory cells involves oxidation, diffusion, and photolithographic etching processes conventionally used in semiconductor technology. FIG. 1 presents an illustration of the prior art preparation of a memory cell with a select gate. The conventional process involves several steps. First, an insulating layer (e.g., doped or undoped silicon dioxide) is grown on a semiconductor substrate of one polarity 100. Next a first conductive layer 120 is applied and etched on the surface of the substrate between areas where source and drain regions of opposite polarity from the substrate 100 are to be formed, i.e., a FAMOS device region, FIGS. 1(a) and 1(b). A second insulating layer 130 is then grown over the conductive layer of the FAMOS transistor region, FIG. 1(c). Then an insulating layer is grown at a second site on the surface of the substrate between areas where source and drain regions of opposite polarity from the substrate 100 are to be formed, i.e., the select gate region, FIG. 1(c). For example, an silicon dioxide/silicon nitride/silicon dioxide ("ONO") layer is masked and etched over the select gate region, followed by an oxidation to create the gate oxide 180 over the select gate region. Finally, a second conductive layer 140 is applied and etched over the FAMOS transistor region and a first conductive layer 140 over the select gate region, FIGS. 1(d)-(g).
In comparison to the select gate in the process described above, the FAMOS transistor region gets an additional insulating layer and an additional conductive layer. Further, the second conductive layer etch generally consists of two separate etches. First, the conductive regions above the FAMOS transistor site and the select gate region are defined. The conductive regions above the FAMOS transistor region and the select gate region (i.e., the single conductive layer region) are masked 170 (i.e., covered with a photosensitive emulsion or photoresist after development of the photoresist) so that the area adjacent to the FAMOS transistor site is exposed. The exposed area is then etched to remove conductive material from the area adjacent to the FAMOS transistor site, FIG. 1(e). For explanatory purposes, this etch is referred to as the "FAMOS etch". With its additional conductive layer, the FAMOS transistor site is significantly higher or thicker than the single conductive layer on the substrate surrounding the select gate site. To assure that residual conductive material is removed from the substrate, the FAMOS etch of the material adjacent to the FAMOS transistor site must overlap into the region of the select gate transistor site. As illustrated in FIG. 1(e), the different thickness of material (i.e., the double layer FAMOS region versus the single layer select gate region), causes the substrate subjected to the first etch around the select gate region to be undesirably gouged or etched 150.
The next conductive layer etch defines the select gate site, FIG. 1(f). For this etch, the FAMOS region and the select gate site are masked 190. To assure that the select gate is not defined adjacent to the gouge, the mask 190 does not extend into or cover the entire gouged-substrate area. As illustrated in FIG. 1(f), when the unmasked area is etched to define the select gate, the substrate is susceptible to secondary gouging 160 from the select gate etch. The completed cell thus consists of a FAMOS transistor with stacked conductive layers separated by an insulating layer and a select gate transistor that is a single conductive layer, FIG. 1(f). The substrate on which the transistors rest are gouged at an area adjacent to the FAMOS device and the select gate.
M. Momodomi, et al., "New Device Technologies for 5V-Only $ Mb EEPROM with NAND Structure Cell", IEDM Tech. Dig., pp. 412-15, 1988 ("Momodomi"), describes an EEPROM memory cell with select gate. The memory cell uses Fowler-Nordheim tunneling for programming and erasing (i.e., FLOTOX). Momodomi describes a cell made up of eight memory transistors and two select transistors. The memory transistors are FAMOS transistors. The select transistors are comprised of two stacked conducting layers separated by an insulating layer. The select transistor described in Momodomi consists of a floating conducting layer similar to the floating conducting layer of a FAMOS device. Momodomi does not specifically describe the fabrication of the memory cell.
The gouge in the substrate produced by the prior art process has several negative effects. First, the gouge increases the resistance along the read and programming paths which reduces the read current, decreases the programmed voltage, and may increase program time. Secondly, the gouge potentially creates crystalline defects such as dislocations, associated with stress at the sharp corners of the gouge or the roughened substrate surface. These defects can lead to leakage to the substrate or across one of the transistors which can cause functional failure. The gouge also causes severe topology. A significant step height exists between the top of the FAMOS stack to the bottom of the gouge. Later in the process, the topology is hard to fill with a void-free insulator and the non-planar surface makes patterning subsequent layers difficult. Further, oxide spacers will be formed at the interior of the gouge edges. Obtaining an electrical connection beneath these spacers establishes a minimum thermal cycle for the process that may prevent optimization. Finally, the transistors must be spaced away from the gouge, because a transistor spaced close to the gouge will experience degraded performance. The amount of spacing must accommodate the possibility of misalignment between masking layers and is, therefore, larger than the theoretical minimum. The spacing requirements will increase the size of the cell. In addition to the gouge, an oxide spacer may be created at the FAMOS-etch mask edge in the select gate region, see FIG. 1(e). During the subsequent select gate etch, the oxide spacer will not be removed. The oxide spacer may mask a residual poly stringer. The presence of the residual poly stringer limits layout options by preventing the intersection of the FAMOS-etch mask (photoresist layer 170) and the select gate mask (photoresist layer 190). The oxide spacer will also contribute to the resistance of the read/programming path in the cell.
To overcome the problems described, there is a need for a non-volatile memory cell with a FAMOS transistor and a select transistor and a process for making the described cell whereby the cell substrate is not gouged as a result of a series of etching steps.